摘要
提出了一种基于分层结构的内建自测试(BIST)设计方法—3DC-BIST(3D Circuit-BIST)。根据3D芯片的绑定前测试和绑定后测试阶段,针对3D芯片除底层外的各层电路结构,采用传统方法,设计用于绑定前测试的相应BIST结构;针对3D芯片底层电路结构与整体结构,通过向量调整技术,设计既能用于底层电路绑定前测试又能用于整体3D芯片绑定后测试的BIST结构。给出了一种针对3D芯片的BIST设计方法,与传统方法相比减少了面积开销。实验结果表明该结构在实现与传统3D BIST方法同样故障覆盖率的条件下,3D平面面积开销相比传统设计方法减少了6.41%。
A built-in self test（BIST） design method─3DC-BIST（3D Circuit-BIST） based on hierarchical architecture is proposed.According to the two stage of before bonding and after bonding test,aiming at the non-bottom circuits in 3D chips,the traditional methods is used to design the corresponding BIST structure,and the circuits before bonding is test.Then,aiming at the bottom circuit and the overall circuit in 3D chips,the BIST that can both test the bottom circuit before bonding and test the overall circuit after bonding by adjusting the test vectors is designed.A BIST structure for 3D chips is presented,and comparing with the traditional methods the overhead in area is reduced.The experimental results show that the method can reach the same fault coverage compared to the traditional 3D BIST method,the average surface cost of 3D chip reduces 6.41% compared to traditional 3D BIST method.
出处
《电子测量与仪器学报》
CSCD
2012年第3期215-222,共8页
Journal of Electronic Measurement and Instrumentation
基金
国家自然科学基金(No.61106037)
博士点基金新教师项目(200803591033)
关键词
3D芯片
绑定前测试
绑定后测试
内建自测试
3D chips
before bounding test
after bounding test
built-in self test
