摘要
本文在分析MOSFET衬底电流原理的基础上 ,提出了一种新型抗热载流子退化效应的CMOS数字电路结构 .即通过在受热载流子退化效应较严重的NMOSFET漏极串联一肖特基二级管 ,来减小其所受电应力 .经SPICE及电路可靠性模拟软件BERT2 .0对倒相器的模拟结果表明 :该结构使衬底电流降低约 5 0 % ,器件的热载流子退化效应明显改善而不会增加电路延迟 ;且该电路结构中肖特基二级管可在NMOSFET漏极直接制作肖特基金半接触来方便地实现 ,工艺简明可行又无须增加芯片面积 .
Based on analysis of the principle of substrate current of MOSFETs,a new hot carriers resistant structure of CMOS digital circuits is proposed.This technique lowers the electric stress by adding a schottky diode in series with the drain of the NMOSFET suffered heavily from hot carrier degradation.The simulation results of CMOS inverter of this structure by SPICE and the berkeley reliability tools BERT 2 0 show that its substrate current is suppressed to about 50% of its original value and good hot carriers resistant behaviors are obtained without adding any extra delay.Also,the added schottky diode can be easily realized by schottky contact in the drain of the NMOSFET,which does not add chip area.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2000年第5期65-67,共3页
Acta Electronica Sinica
基金
国家自然科学基金资助课题
国防预研项目资助课题
关键词
MOSFET衬底电流
热载流子效应
CMOS电路结构
MOSFET substrate current
Hot carrier effect
BERT
schottky contact
new CMOS circuits structure
