摘要
本文介绍了一种适用于高速差分数据接收的CMOS串并转换电路,该电路主要由时钟电路、1:2数据分割电路和1:5分接器组成。采用65nm工艺,仿真结果表明,在数据传输速度为5Gb/s时功耗为12mW。
In this paper,the implementation of a parallel-to-serial conversion circuit is presented.The circuits is composed of three main blocks,clock distribution network,two high speed 1：2 slicer and two 1：5 DEMUX.The proposed circuit is realized in a standard 65nm CMOS process.The simulation results show that total power consumption of 12 mW in 5Gb/s data rates under normal temperature.
出处
《中国集成电路》
2012年第4期57-60,68,共5页
China lntegrated Circuit
关键词
光纤通信
数据接收
串并转换
分接器
Optical transmission
Receiver
Parallel-to-serial Conversion
DEMUX
