摘要
由于模拟集成电路的性能与版图设计密切相关,着重介绍了CMOS模拟电路版图设计的一般思路,优化器件结构和平面布局使寄生效应对电路性能的影响降至最低。
Because the performance commonconsideration about layout design of analog circuit have great relationship with layout design, of CMOS analog circuit is introduced. Optimization of device structure and plane floorplan degrade the effect of parasitical to the minimum for circuit performance.
出处
《微处理机》
2012年第3期4-6,共3页
Microprocessors
关键词
模拟电路
版图设计
寄生电容
Analog circuit
Layout design
Parasitic capacitance
