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低功耗脑深部电刺激器(DBS)硬件电路设计 被引量:1

Hardware Circuit Design of Low-power DBS Internal Simulation System
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摘要 脑深部电刺激(DBS)疗法具有对脑结构损伤小、并发症少、可逆等优点,在神经外科治疗中发挥着重要的作用;根据医学应用需要,给出了一种低功耗的脑深部电刺激器设计方案,重点论述了DBS体内刺激部分的硬件电路设计;采用低功耗短距离射频通信模块nRF24L01实现DBS系统的可靠数据传输;采用低频唤醒模块ATA5283实现系统的任意时刻唤醒以降低功耗;采用单片机AT-mega48、运算放大器TLV2404实现压控恒流输出;实验结果表明,刺激脉冲输出正常,系统功耗较低,电路设计具有一定的实用性和推广价值。 Since Deep Brain Stimulation (DBS) technique has much less brain destruction and much less syndrome and is reversible, it has already been proved that DBS has an important functional role in the treatment of neurosurgery. According to medical applications, this paper describes a design scheme of low power consumption, and largely discusses hardware circuit design of the DBS internal stimulation sys tern. Considering the high reliability during communication and the power consumption, nRF24L01 RF communication module is used for transmitting data and ATA5283 low frequency awaking module is used for the awaking at any time in the circuit design. Meanwhile, AT- mega48 MCU module and amplifier TLV2404 are used for providing stable output current. The test results show that stimulation pulses are correct and power consumption is lower and The technology and methods adopted in the circuit are practical and worthy of using abroad.
出处 《计算机测量与控制》 CSCD 北大核心 2012年第8期2210-2212,2247,共4页 Computer Measurement &Control
关键词 DBS 射频通信 低功耗 单片机 DBS RF communicatiom low power MCU
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