摘要
UART控制器是计算机串行通信子系统和电信领域广泛使用的设备;针对工程应用中UART内部FIFO空间不能满足需求的问题,结合UART的特点以及FPGA设计可移植性的优势,提出一种基于FPGA芯片的嵌入式UART IP核设计方法;对于接收和发送通道分别配置有256字节的先进先出堆栈,有效减小了对CPU资源的占用,提高了IP核性能;而且在每帧数据之间增加字间隔,并通过编程设置字间隔长度,可有效解决不同设备间处理数据速度有差异的问题;利用硬件描述语言VHDL来实现设计,并完成了UART的功能和时序仿真,结果显示设计满足要求,具有良好的使用价值。
UART Controller is a serial communication interface widely used in computer serial communication subsystem and telecommu- nication fields. Based on the fact that during the actual engineering applications for UART, internal FIFO space can＇ t meet demand, it pro- posed a FPGA--based embedded UART IP core design method. It configured 256 bytes of FIFO respectively for the receive and transmit channels. The interval between sent words can he programmed. It used hardware description language VHDL to design the UART modules and completed functional and timing simulation. Simulation results show that the design meets the requirements.
出处
《计算机测量与控制》
CSCD
北大核心
2012年第8期2251-2253,共3页
Computer Measurement &Control
基金
航空科学基金(2010ZC53036)
