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快速锁定的宽频带CMOS锁相环设计 被引量:5

Design of a fast-lock CMOS phase-locked loop with wide band width
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摘要 设计了一种可快速锁定的宽频带CMOS电荷泵锁相环电路.通过增加一个自适应带宽控制模块,当锁相环处于捕捉状态时,增加环路带宽实现快速锁定;锁相环接近锁定状态时,减小带宽,保证环路的稳定性和减小杂散.同时还设计了能工作在宽频率范围的压控振荡器.该锁相环基于0.25μm CMOS工艺,供电电压为2.5V时,工作范围在960~2 560MHz,功耗为8.9~23.2mW,锁定时间小于12μs. A Fast-lock phase-locked loop(PLL)with a wide band width was designed based on CMOS process.By adding a bandwidth-control module,a wider bandwidth was used during transient to reduce lock time.While a phase lock was attained,the bandwidth was shifted to a smaller value for optimum spectrum.A wide-range voltage-controlled oscillator(VCO)was also designed in the circuit.The PLL can operate in the frequency range from 960to 2 560MHz with a setting time of less than 12 μs,and the power dissipation is from 8.9to 23.2mW at a 2.5Vsupply.
出处 《华中科技大学学报(自然科学版)》 EI CAS CSCD 北大核心 2012年第7期71-74,共4页 Journal of Huazhong University of Science and Technology(Natural Science Edition)
基金 湖北省自然科学基金资助项目(2010CDB02706) 华中科技大学自主创新基金资助项目(C2009Q060)
关键词 锁相环 快速锁定 环形压控振荡器 宽频带 相位噪声 phase-locked loop fast lock ring voltage-controlled oscillator wide rage phase noise
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参考文献10

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同被引文献20

  • 1王照峰,王仕成,苏德伦.锁相环电路的基本概念及应用研究[J].电气应用,2005,24(8). 被引量:46
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  • 3Wei-Hao Chiu, Tai-Shun Chan, Tsung-Hsien LirL A 5. 5-GHz 16-mW fast-locking frequency synthesizer in 0. 18-μm CMOS[C]//IEEE Asian Solid-State Circuits Conference. Korea: IEEE, 2007 : 4-17.
  • 4王小松.宽带高性能CMOS频率综合器研究[D].北京:中国科学院研究生院,2010.
  • 5毕查德拉扎维.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2011:247-249.
  • 6Keliu Shu, Edgar Sanchez-Sinecio. Cmos pll synthesiz- ers analysis and design [M]. Berlin: Springer Science, 2005:58-60.
  • 7刘俊杰.全数字锁相环电路的设计与实现[D] .成都:电子科技大学,2011.
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  • 9赵宇浩,陈军宁,吴秀龙,梅振飞,徐太龙,鲁士滨.2.4GHz低相位噪声CMOS负阻LC压控振荡器设计[J].计算机技术与发展,2008,18(2):170-172. 被引量:2
  • 10阴亚东,阎跃鹏,梁伟伟,杜占坤.A fast lock frequency synthesizer using an improved adaptive frequency calibration[J].Journal of Semiconductors,2010,31(6):131-136. 被引量:2

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