摘要
设计了一款简易逻辑分析仪。采用数字信号采集以及数字示波器存储显示原理,以ARM芯片S3C44B0X与FPGA芯片EPC2Q208C6组成系统核心。该设计由数字信号发生器、数据采集、触发控制、数据存储、显示等模块构成。该设计具有多级采样时钟和32路采样通道,具有测试速率高、多输入通道、触发方式多等优点。采用VHDL编程,在Quartus Ⅱ下进行编译、综合、仿真,然后下载到FPGA器件上成功实现了逻辑分析的常规功能,验证了该设计的正确性。
A simple logic analyzer is designed based on the digital signal acquisition and the storage display principle of digital oscilloscope,including the modules of digital signal generator,data acquisition,trigger control,data storage,display,etc.It takes ARM chip S3C44B0X and FPGA chip EPC2Q208C6 as its system core and adopts multi-stage sampling clock and 32 sampling channels,with high test speed,multiple input channels and multiple trigger modes.The program is written with VHDL,and compiled,integrated and simulated in Quartus Ⅱ.It is downloaded to FPGA device and the general functions of logical analyzer are successfully implemented,which verifies the correctness of the design.
出处
《电力自动化设备》
EI
CSCD
北大核心
2012年第9期149-152,共4页
Electric Power Automation Equipment
基金
四川省教育厅重点科研项目(2006-A091)~~
