摘要
随着集成电路日新月异的发展,当半导体器件工艺进展到纳米级别后,传统的二维领域封装已渐渐不能满足电路高性能、低功耗与高可靠性的要求。为解决这一问题,三维封装成为了未来封装发展的主流。文章简要介绍了三维封装的工艺流程,并重点介绍了硅通孔技术的现阶段在CSP领域的应用,以及其未来的发展方向。
With the development of now day integrated circuit, the traditional 2D packaging can not satisfy the requirement of high function, low power and high reliability when the semiconductor device develops into nano level. To solve the problem, 3D packaging becomes the mainstream of future package. In this paper, authors introduce the process flow of 3D package and emphasize the through silicon via （TSV） technology using in CSP area and the further development＇s direction.
出处
《电子与封装》
2012年第9期18-23,共6页
Electronics & Packaging
