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针对多簇架构的软件流水调度框架设计与实现

Design and Implementation of the Software Pipelining Scheduling Framework for Multi-cluster Architecture
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摘要 介绍基于编译基础设施IMPACT实现针对BWDSP100多簇体系结构特点软件流水调度框架.该调度框架能充分发掘多簇体系架构的硬件资源,在DSP特性应用程序上能有较好性能提升. This article describes the framework of the software pipelining scheduling for BWDSP100 multi-cluster architecture which is based on compile basic facilities IMPACT. The framewokr can fully exploit the hardware resources of Multi-cluster architecture and get better performance improvement in the application of the DSP features.
作者 冯玉谦 郑启龙 陈思灵 付和萍
机构地区 中国科学技术大学计算机科学与技术学院 安徽省高性能计算重点实验室
出处 《计算机系统应用》 2013年第2期76-79,共4页 Computer Systems & Applications
关键词 IMPACT 软件流水 多簇 DSP IMPACT software pipelining multi-cluster DSP
分类号 TP311.52 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献7

  • 1Lam MS. Software pipelinmg: An effective scheduling technique for VLIW machines. Proc. of the SIGPLAN88 Conference on Programming Language Design and Implementation, June 1988. 318-328.
  • 2Chang PP, Mahkle SA, Chen WY, Water N J, HWU WW. IMPACT: Art architectural framework for multpile- instruction-issue prcoessors. 18th Annual International Symposium on Computer Architecture, Bacrelona: ACM Press, 1998: 408---417.
  • 3Fisher JA.Very Long Instruction Word Architectures and the ELI- 512;1983,11(3): 140-150.
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  • 5Philip B, Steven PS. Gibbons Efficient instruction sched- uling for a pipelined architecture. ACM SIGPLAN Notices, 1986,21(7):11-16.
  • 6雷一鸣,洪一,徐云,姜海涛.一种基于寄存器压力的VLIWDSP分簇算法[J].计算机应用,2010,30(1):274-276. 被引量：9
  • 7Raul BR. Iterative modulo scheduling: An algorithm for soRware pipelining loopsl. Proc. of the 27th Annual Int'l Symp on Mieroarehitecturel New York: ACM Press, 1994: 63-71.

二级参考文献7

  • 1DESOLI G. Instruction assignment for clustered VLIW DSP compilers: A new approach[ EB/OL]. [ 2009 - 06 - 20]. http://www. hpl. hp. com/techreports/98/HPL-98-13, pdf.
  • 2LAPINSKII V, JACOME M F, VECIANA G A. Cluster assignment for high performance embedded VLIW processors[ J]. ACM Transactions on Design Automation of Electronic Systems, 2002, 7(3) : 430 - 454.
  • 3HWU W W. The IMPACT Research Group[ EB/OL]. [ 2009 - 03 - 15]. http://impact, crhc. illinois, edu/.
  • 4RAU B R. Iterative modulo scheduling: An algorithm for software pipelining loops[ C]//Proceedings of the 27th International Symposium on Microarchitecture. New York: ACM, 1994:63 - 74.
  • 5CHOW F. Register allocation by priority-based coloring[ J]. ACM SIGPLAN Notices, 1984, 19(6) : 222 -232.
  • 6PHILIP B. Gibbons Efficient instruction scheduling for a pipelined architecture[ J]. ACM SIGPLAN Notices, 1986, 21 (7) : 11 - 16.
  • 7The Institute for Integrated Signal Processing Systems . DSPstone [ EB/OL]. [ 2009 -03 -20]. http://www, ert. rwth-aaehen, de/ Projekte/Tools/DSPSTONE/dspstone htmt.

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计算机系统应用
2013年 第2期

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