摘要
该文在高级加密标准(AES)快速算法的基础上,设计了一组基于可配置处理器NiosII上的扩展指令,用于IEEE802.15.4标准媒体访问控制层中基于AES算法的计数器模式和密码分组链接消息验证码(AES-CCM)协议的硬件加速。该文首先推导出快速算法中用于轮变换的查找表与S盒的逻辑关系,然后通过复合域变换方法用硬件电路实现S盒的计算,从而消除了支撑扩展指令集的硬件逻辑对片上存储空间的消耗。同时给出该协议基于查表法的扩展指令集和协处理器的设计方案,并在EP2C35芯片上进行实现和对比。该方案仅消耗223个逻辑单元(LE),吞吐量为668.7 kbps,时钟周期数比软件算法加速174.6倍,芯片面积仅为协处理器方案的9.5%,显著降低了无线传感网节点设备的成本和功耗。
An instruction set extension for Counter mode with Cipher block chaining Message authentication code protocol using Advanced Eneryption Standard algorithm （AES-CCM） protocol in IEEE802.15.4 is presented based on AES fast algorithms and NiosII processor. The logical relationship between the lookup table used for round transformation and S-box is derived, then the S-box value is calculated with composite field transform method in hardware circuit, thereby eliminated the consumption of on-chip memory. The scheme is verified on EP2C35 chip, and the design and experimental data of look-up table method of the instruction set extension design and co-processor are also proposed for compare. This schemes increases the speedup by 174.6 times than software implementation, only uses 223 logic elements as 9.5% of coprocessor, throughput achieves 668.7 kbps, and reduces significantly the cost and power consumption of wireless sensor network node equipments.
出处
《电子与信息学报》
EI
CSCD
北大核心
2013年第2期335-340,共6页
Journal of Electronics & Information Technology
基金
国家自然科学基金(61070015)
广东省自然科学基金团队项目(10351806001000000)资助课题
