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H.264/AVC中整数DCT变换量化模块的Verilog设计 被引量:1

Verilog Design of Integer DCT and Quantization Module in H.264/AVC
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摘要 H.264/AVC视频压缩标准采用了4×4整数DCT变换和量化方法,避免了数据失配并提高了精度,具有较高的编码效率。本文分析H.264整数DCT变换和量化算法,将DCT变换转换为两次快速蝶形运算,减少了计算量,并用Verilog硬件描述语言编程实现整数DCT变换和量化功能,利用QuartusII进行综合和仿真,得到正确的结果。本设计具有54.54MHz的时钟频率、较低的资源消耗和功耗。 The video compression standard H.264/AVC uses 4×4 integer DCT and quantization methods,which avoid data mismatch and improve data accuracy,thus has high compression efficiency.This paper analyzes the algorithm of integer DCT and quantization in H.264.By transforming DCT into two quick butterfly computations,it reduces algorithm complexity and makes it easer to realize.The synthesis and simulation by QuartusII show the correct results.The design is of 54.54MHz high clock frequency,low resource usage and low power dissipation.
作者 沈劲桐 张卫
出处 《计算机与现代化》 2013年第2期108-112,116,共6页 Computer and Modernization
基金 广东省科技计划省国际合作项目(2010B050900016)
关键词 H 264 AVC 整数DCT 量化 VERILOG HDL H.264/AVC integer DCT quantization Verilog HDL
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参考文献15

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