摘要
祖冲之(ZUC)算法是我国自主设计的流密码算法,该算法在2011年12月被3GPP LTE采纳为国际加密标准,即第四代移动通信加密标准。目前,基于祖冲之算法的FPGA设计在国内外引起了广泛的关注。本文在实现祖冲之加/解密系统的基础上,提出了一种资源优化的祖冲之算法的硬件实现方法。该方法优化了原祖冲之算法中对S盒进行并行寻址的逻辑,采用分时复用的寻址逻辑。经过仿真与综合,结果表明本文提出的方法大幅降低了系统的资源开销,当复用的寻址逻辑最多时,系统的资源开销可以降低45%。
The ZUC algorithm is a stream cipher designed by Chinese cryptogists, and is accepted as the international encryption standard for the 4G mobile communication on December in 2011. Recently the FPGA design methods of the ZUC algorithm have been widely researched. This paper proposed a resource-optimized implementation method of the ZUC algorithm. The proposed method optimized the parallel addressing logic of the original algorithm by using time division multiplexing method. After simulation and synthesis, the results show that the proposed method can greatly reduce system resource overhead. When the number of multiplexing is the largest, the reduction of system resource overhead is up to 45%.
出处
《科学技术与工程》
北大核心
2013年第5期1330-1334,共5页
Science Technology and Engineering
基金
核高基重大专项基金(2009ZX01034-002-004-007(002))资助
关键词
祖冲之算法
加解密
FPGA
资源优化
ZUC algorithm
Encryption and decryption
Field Programmable Gate Arrays
resource optimization
