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硅通孔尺寸与材料对热应力的影响 被引量:8

Influences of Size and Material of Through-Silicon Via on Thermo-mechanical Stress
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摘要 通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。 The thermo-mechanical stress of both single Through-Silicon Via (TSV) and two-chip-stacked package was investigated with the use of finite element analysis. Stress distributions were demonstrated to be affected by filling materials (copper and tungsten), and the advantages of tungsten-filled TSVs on thermal stress were found. Stress values were proved to be relevant to TSV sizes, such as TSV diameters and aspect ratios of the silicon thickness and the TSV diameter. In order to find the material collocation which has the smallest thermal stress, two-chip-stacked model was applied to simulate the stress in common used materials. It is found that the structure using silicon dioxide as the insulation layer, tungsten as the filling and tin (Sn) as the bonding materials yields the best mechanical performance. Besides, the combination of copper, ABF and tin also performs well in stress.
出处 《半导体光电》 CAS CSCD 北大核心 2013年第2期255-258,共4页 Semiconductor Optoelectronics
基金 国家自然科学基金项目(61274104)
关键词 硅通孔 热应力 三维集成封装 有限元分析 TSV thermal-mechanical stress 3D integration finite element analysis
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参考文献7

  • 1Kim Y,Kang S K,Kim S D,et al.Wafer warpageanalysis of stacked wafers for 3D integration [ J].Microelectron.Eng.,2012,89:46-49.
  • 2Ryu S,Lu K,Zhang X,et al.Impact of near-surfacethermal stresses on interfacial reliability of through-silicon-vias for 3-D interconnects![J].IEEE Trans,onDevice and Materials Reliability? 2011,11(1):35-43.
  • 3Sun P,Andersson C,Wei X,et al.High temperatureaging study of intermetallic compound formation of Sn-3.5Ag and Sn-4.0Ag-0.5Cu solders on electroless Ni(P) metallization [J].J.Alloys and Compounds,2006,425(1/2):191-199.
  • 4Liu X,Chen Q,Dixit P,et al.Failure mechanisms andoptimum design for electroplated copper through-silicon vias ( TSV) [C]//Proc.59th ElectronicComponents and Technol.Conf.,2009:624-629.
  • 5Haq J,Vogt B D,Raupp G B,et al.Finite elementmodeling of temporary bonding systems for flexiblemicroelectronics fabrication[J].Microelectron.Eng.,2012,94:18-25.
  • 6Read D T,Cheng Y W,Geiss R.Morphology,microstructure,and mechanical properties of a copperelectrodeposit[J],Microelectron.Eng.,2004,75(1):63-70.
  • 7Shen L C,Chien C W,Cheng H C,et al.Developmentof three-dimensional chip stacking technology using aclamped through-silicon via interconnection [ J].Microelectron.Reliability,2010*50(4):489-497.

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