期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

应用于硅通孔的深孔铜电镀工艺优化 被引量：4

Optimization for Copper Electrodeposition Process Applied in Through Silicon Via
原文传递
导出
摘要 对高深宽比(6∶1)深孔的铜电镀工艺进行了大量实验研究,通过调整电镀时间和电流密度,以及优化电镀前后的样品表面处理以及清洗方式,最终得到稳定、高效的电镀工艺方法及良好的镀层质量,其研究结果可在MEMS封装领域中得到广泛应用。 A copper electrodeposition process for creating high aspect-ratio （6 ： 1） TSVs was studied. The process produces defect-free via fillings, which are key to the successful implementation of high quality and high reliability 3D interconnections. The key aspects of the electrodeposition process and a number of optimization approaches were discussed.
作者 王爱博
机构地区 天津大学精密仪器与光电子工程学院
出处 《热加工工艺》 CSCD 北大核心 2013年第14期93-96,共4页 Hot Working Technology
基金 天津市科委资助项目(11ZCKFGX01500) 国家自然科学青年基金资助项目(61006074)
关键词 TSV 3D封装 铜电镀 through silicon via（TSV） 3D integration copper electrodeposition
分类号 TN405 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献11

  • 1Song Chongshen, Wang Zheyao, Liu Litian. Bottom-up copper electroplating using transfer for fabrication of high aspect-ratio through-silicon vias[J]. Journal of Microelectronic Engineering, 2010,87:510-513.
  • 2Xavier Gagnard, Thierry Mourie. Through silicon via:from the CMOS imager sensor wafer level package to the 3D integration [J]. Journal of Mieroeleetronic Engineering,2010,87 : 470-476.
  • 3Tsai Tzuhsuan, Huang Juihsitmg. Electrochemical investigations for copper eectrodeposition of through-silicon via ). Journal of Microelectronic Engineering, 2010,88:195-199.
  • 4朱健.3D堆叠技术及TSV技术[J].固体电子学研究与进展,2012,32(1):73-77. 被引量：19
  • 5VanOlmen J. 3D Stacked IC demonstration using a Through Silicon Via First approach [C] // Technical Digest of the International Electron Device Meeting. San Francisco:CA, 2007.
  • 6赵璋,童志义.3D-TSV技术——延续摩尔定律的有效通途[J].电子工业专用设备,2011,40(3):10-16. 被引量：16
  • 7Banqiu. High aspect ratio silicon etch: a review [J]. Journal of Applied Physicsvo1,2010, 108:051101-051120.
  • 8Spiesshoefer S. Copper electroplating to fill blind vias for three-dimensional integration [J]. Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2006,24 : 1277-1282.
  • 9Wolf M J, Dretschkow T, Wunderle B, et al. High Aspect Ratio TSV Copper Filling with Different Seed Layers [C] // Electronic Components and Technology Conference. Florida: ,2008.
  • 10Junyi Li, Wang Hong, Wang Huiyi, et al. Design and Fabrication of Cu-TSV Free-standing Specimen for Uniaxial Micro-tensile Test [C] // 2011 International Symposium on Advanced Packaging Materials (APM 2011 ). Xiamen: ,2011.

二级参考文献18

共引文献34

同被引文献21

  • 1Ranganathan N, Prasad K, Balasubramanian N, et al. High Aspect Ratio Through-Wafer Interconnect for Three Dimen- sional Integrated Circuits [ C ] . 2005 Electronic Components and Technology Conference, FL: Lake Buena Vista, 2005 : 343 - 348.
  • 2Alsarawi S F, Abbott d, Franzon P D. A Review of 3D Packag- ing Technology[ J ] . IEEE Transactions on Components, Pack- ing and Manufacturing Technology, 1998,21 ( 1 ) :2 - 14.
  • 3Garrou P, Bower C, Ramm P. Hand Book of 3D Integration [ M]. Weinheim : Wiley-Vch Verlag Gmbh&Cokgaa, 2008 : 25 - 40.
  • 4Ramm P, Wolf M J, Klumpp A, et al. Through Silicon Via Technology-Processes and Reliability for Wafer-Level 3D System Integration [ C ]. 2008 Electronic Components and Technology Conference, FL: Lake Buena, 2008 : 841 - 846.
  • 5Liu X, Chen Q, Pradeep D et al. Failure Mechanisms and Op- timum Design for Electroplated Copper Through-Silicon Vias ( TSV ) [ C ]. 2009 Electronic Components and Technology Conference, CA : San Diego, 2009 : 624 - 629.
  • 6Kawano M,Takahashi N, Kurita Y, et al. Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer [ J ]. IEEE Transactions on Electron Devices, 2008, 55(7) : 1614 - 1620.
  • 7Henry D, Baillin X, Lapras V, et al. Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon [ C ]. 2007 Electronic Components and Technology Conference, NV : Reno, 2007 : 830 - 835.
  • 8Pradeep D, Tapani V, Sami Vet al. Fabrication and Electri- cal Characterization of High Aspect Ratio Poly-Silicon Filled Through-Silicon Vias[J]. Journal of Micromechanic and Mi- croengineering, 2012,22 (5) : 1 - 9.
  • 9Seong J O, Chunho K, Daniel F Baldwin. High Density, High Aspect Ratio Through-Wafer Electrical Interconnect Vias for MEMS Packaging[ J]. IEEE Transaction on Advanced Pack- aging,2003,26(3) :302 - 309.
  • 10Mcauley S A, Ashraf H, Atabo L, et al. Silicon Micmmachin- ing Using a High-Density Plasma Source [ J ]. Journal of Physics D: Applied Physics, 2001,34(18) : 2769 - 2774.

引证文献4

二级引证文献15

热加工工艺
2013年 第14期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部