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基于V93000的SoC中端口非测试复用的ADC和DAC IP核性能测试方案 被引量:11

Performance Parameter Testing for ADC and DAC IP Cores Without I/O Multiplexing in SoC Using Verigy 93000
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摘要 SoC(System-on-a-Chip)芯片设计中,由于芯片测试引脚数目的限制以及基于芯片性能的考虑,通常有一些端口不能进行测试复用的IP(Intellectual Property)核将不可避免地被集成在SoC芯片当中.对于端口非测试复用IP核,由于其端口不能被直接连接到ATE(Automatic Test Equipment)设备的测试通道上,由此,对端口非测试复用IP核的测试将是对SoC芯片进行测试的一个重要挑战.在本文当中,我们分别提出了一种基于V93000测试仪对端口非测试复用ADC(Analog-to-Digital Converter)以及DAC(Digita-l to-Analog Converter)IP核的性能参数测试方法.对于端口非测试复用ADC和DAC IP核,首先分别为他们开发测试程序并利用V93000通过SoC芯片的EMIF(External Memory Interface)总线对其进行配置.在对ADC和DAC IP核进行配置以后,就可以通过V93000捕获ADC IP核采样得到的数字代码以及通过V93000采样DAC IP核转换得到的模拟电压值,并由此计算ADC以及DAC IP核的性能参数.实验结果表明,本文分别提出的针对端口非测试复用ADC以及DAC IP核测试方案非常有效. IP cores without I/O multiplexing are typically unavoidable to be embedded into SoC due to the necessary considerations such as pin constraint and performance optimization during the design stage.Hence,one of the serious challenges for SoC testing is how to effectively test IP cores without I/O multiplexing because the ports of IP cores without I/O multiplexing cannot be directly connected to the ATE channels.In this paper,we propose test methods for ADC and DAC IP cores without I/O multiplexing using V93000 ATE respectively.In order to test the ADC and DAC IP cores without I/O multiplexing,test programs are firstly developed and loaded into V93000 to configure the two cores via EMIF bus.Then the digital codes and the analog voltage values respectively converted by ADC and DAC IP cores of SoC are captured by V93000 for performance parameter calculation.Experimental results show that the proposed methods are effective.
出处 《电子学报》 EI CAS CSCD 北大核心 2013年第7期1358-1364,共7页 Acta Electronica Sinica
基金 中国博士后科学基金特别资助(No.2012T50092) 中国博士后科学基金面上资助(No.2011M500321)
关键词 片上系统 模数转换器 数模转换器 V93000测试仪 性能参数 System-on-a-Chip ADC DAC V93000 ATE performance parameter
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  • 1熊志辉,李思昆,陈吉华,王海力,边计年.一种基于层次平台的SoC系统设计方法[J].电子学报,2004,32(11):1815-1819. 被引量:9
  • 2S Sarkar, S Chandar G,S Shinde. Effective IP reuse for high quality SOC design [ A ]. Proceedings of IEEE International SOC Conference[ C]. Washington DC: IEEE Computer Soci- ety,2005.217 - 224.
  • 3罗胜钦,马萧萧,陆忆.基于改进的NSGA遗传算法的SOC软硬件划分方法[J].电子学报,2009,37(11):2595-2599. 被引量:15
  • 4胡瑜,韩银和,李晓维.SOC可测试性设计与测试技术[J].计算机研究与发展,2005,42(1):153-162. 被引量:42
  • 5P R Femando, S Katkoori, D Keymeulen, R Zebulum,A Sto- ica. Customizable FPGA IP core implementation of a gener-al-purpose genetic algorithm engine [ J]. IEEE Transactions on Evolutionary Computation,2010,14(1) : 133 - 149.
  • 6A Deshpande. Verification of IP-Core based SoC' s[ A]. Pro- ceedings of International Symposium on Quality Electronic Design[ C]. Washington DC: IEEE Computer Society, 2008. 433 - 436.
  • 7邓立宝,乔立岩,俞洋,彭喜元.一种改进的层次化SOCs并行测试封装扫描单元[J].电子学报,2012,40(5):949-954. 被引量:3
  • 8M Nahvi, A Ivanov. Indirect test architecture for SoCtesting [J]. IEEE Transactions on Computer-Aided Design of Inte- grated Circuits and Systems,2004,23(7) : 1128 - 1142.
  • 9K George,C-I H Chen. Logic built-in self-test for core-based designs on system-on-a-chip[J].IEEE Transactions on In- saxtrnentation and Measttrement,2009,58(5) :1495 - 1504.
  • 10高雅,刘亚洲.基于V93000的高速模数转换芯片静态性能测试与分析[A].第一届中国微电子计量与测试技术研讨会[C].湖北武汉,2008.22-26.

二级参考文献127

  • 1韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量:27
  • 2Gupta R K, Micheli G D. Hardware-software CO-synthesis for digital systems[J]. IEEE Design & Test of Computer, 1993, 10(3) :29- 41.
  • 3Ernst R, Henkel J, Benner T. Hardware software co-synthesis for micro-controllers [J]. IEEE Design & Test of Computer, 1993,10(4) :64 - 75.
  • 4Kalavade A, Lee E A. The extended partitioning problem: Hardware/software mapping, scheduling and implementationbin selection[ J ]. Design Automation for Embedded System, 1997,2(2) : 125 - 164.
  • 5Niemann R,Marwedel P. Hardware/software partitioning using integer programming[A] .Proceedings of European Design and Test Conference[C]. Paris, 1996.473 - 479.
  • 6Madson J,Grode J, Knudsen P V, et al. LYCOS: The lyngby CO-synthesis system [J]. Design Automation for Embedded System, 1997,2(2) : 195 - 236.
  • 7Grode J, Knudsen P V, J Madsen. Hardware resource allocation for hardware/software partitioning in the LYCOS system[A]. Proceedings of Design Automation and Test in Europe [C]. Paris, 1998.33 - 36.
  • 8Abdenour Azzedine, Jean Diguet. JeanLac Pillippe. Large exploration for HW/SW partitioning of multi-rate and a periodic real-tirne systems[A]. 10^th International Workshop on Hardware/Software Co-Design[ C ]. Colorado, 2002.85 - 90.
  • 9B Knerr,M Holzer,M Rupp. HW/SW partitioning using high level metrics [A]. International Conference on Computing, Communications and Control Technologies (CCCT) [ C ]. Austin,2004.33 - 38.
  • 10Jefrey Horn,Nicholas Nafpliotis,David E Goldberg.A niched Pareto genetic algorithm for multi-objective optimization[A]. Proceedings of the First IEEE Conference on Evolutionary Computation[C]. IEEE World Congress on Computational Intelligence, Orlando, FL, USA, 1994.

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