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传感器网络中图像小波处理的低存储硬件实现 被引量:1

Low storage hardware implementation of image wavelet processing in sensor networks
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摘要 为了适应当前传感器网络中越来越多的图像压缩处理,提出了一种片上低存储离散小波变换(DWT)的超大规模集成电路(VLSI)结构。现今人们周围遍布各种图像采集设备,包括监视器、电脑、手机视频摄像头等,并且人们对图像精度的需求越来越高,使得传统软件处理图像压缩的速度逐渐无法满足人们的需求,这就需要考虑使用硬件处理来进行加速。小波变换常被用于图像的压缩,而采用5/3提升小波技术来进行硬件实现相对比较方便。为减少硬件的片上存储,通过特殊的调度运算方式进行行列并行运算有效降低片上存储需求。该设计进行RTL级仿真并使用SMIC的0.18μm工艺进行综合,结果表明:该调度方法可以大大节省缓存单元,并且在100 MHz时钟下就可以保证对高清图像的快速处理,可以满足当前传感器网络中图像压缩解码的需求。 In order to adapt to increase of the image compression processing in current sensor networks,presents a low storage discrete wavelet transform(DWT) VLSI architecture.Around us scattered all kinds of image acquisition devices,including monitor,computer,mobile video cameras,and growing demand for image precision is higher and higher,which make traditional image compression software processing speed gradually unable to meet the people's needs,so it is necessary to consider using hardware processing to accelerate.Wavelet transform is often used for image compression,while the use of 5/3 lifting wavelet technology to implement hardware is relatively easy.In order to reduce on chip storage of hardware,through special scheduling operations mode to carry out parallel computing of row and column to effectively reduce on-chip storage demand.After RTL-level simulation and synthesized by SMIC 0.18 μm process,the results show that the scheduling method saves cache unit significantly,and with 100 MHz clock,it ensures fast processing on high-definition(HD) images,and meets needs of image compression decoding in current sensor network.
出处 《传感器与微系统》 CSCD 北大核心 2013年第9期16-20,共5页 Transducer and Microsystem Technologies
关键词 传感器 低存储 二维离散小波变换 5 3提升小波 超大规模集成电路 sensor low storage 2D discrete wavelet transform(DWT) 5/3 lifting wavelet very large scale integration(VLSI)
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