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基于自适应比例积分控制的全数字锁相环 被引量:1

All-digital phase-locked loop based on adaptive PI control
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摘要 针对传统锁相环所存在的锁相范围窄、环路带宽和控制参数固定、以及提高锁相速度与减小稳态误差相互制约等问题,提出了一种新型带宽自适应全数字锁相环。该系统采用比例积分控制与自适应控制相结合的复合控制方式,其中自适应控制器可根据锁相过程的鉴频鉴相信息,自动调整数字滤波器的控制参数,实现对环路的实时控制。采用理论分析与硬件电路设计相结合的方法进行了系统设计,并用FPGA予以实现。系统仿真与硬件电路测试结果证实了设计方案的正确性。该锁相环的自由振荡频率可随输入信号频率的变化而改变,具有电路结构简单、锁相范围广、锁定速度快和稳态误差小等特点。 In view of the problems existing in the traditional phase-locked loops (PLL) about narrow locking range, fixed loop bandwidth and control parameters, interaction between increasing locking speed and decreasing static errors, a new type of adaptive-bandwidth with all digital phase-locked loop is proposed, which adopts compound control mode which combines PI control with adaptive control. The adaptive controller would adjust the control parameters of the digital filter according to the detected information of phase and frequency to realize real-time control. The design of the system adopts the method that with a combination of the theoretical analysis and hardware circuit design, and it is implemented by FPGA. The design project is verified by the results from system simulation and hardware circuit test. The free oscillating frequency of the PLL can change along with the input signal frequency. The system has the advantages of simple circuit structure, wide locking range, fast locking speed and small steady state error.
出处 《现代电子技术》 2013年第23期127-129,132,共4页 Modern Electronics Technique
基金 湖南省自然科学基金资助项目(11JJ6054) 湖南省科技厅资助项目(2011GK3224)
关键词 全数字锁相环 自适应 比例积分控制 电子设计自动化 现场可编程门阵列 all digital phase locked-loop adaptive PI control electronic design automation (EDA) FPGA
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