摘要
在雷达信号处理中,为了对低速运动杂波进行有效的抑制,研究了一种杂波速度谱图的建立方法。此杂波速度谱图的建立在FPGA中实现,通过对雷达实际回波数据在FPGA中的处理得到运动杂波速度图。实验结果表明,该方法设计出的杂波速度谱图与仿真结果一致,可以有效地抑制静止和慢速运动的杂波。并且由于超大规模可编程器件的高效处理能力,使其工程实现方便、灵活,具有很强的实用性。
In order to restrain the low-speed clutter effectively in radar signal processing, a method of generating clutter＇s velocity map is studied. This elutter＇s velocity map is realized by FPGA, based on the real radar echo data processing in FPGA. The experimental results show that the elutter＇s velocity map can suppress the stationary and slow moving clutter effectively. By the way, due to the high processing ability of large scale programmable device, its engineering realization is convenient, flexible, and it has a strong practicability.
出处
《电子技术应用》
北大核心
2013年第12期49-51,54,共4页
Application of Electronic Technique
