摘要
提出一种全数字可配置信道分路技术的设计方法,是针对多相阵列FFT算法进行的一种串行结构设计,能够按照分路路数灵活配置多相滤波器组和FFT级数,可支持甚至达到上百路的分路路数。对全数字可配置信道分路的设计方法中涉及到的多相滤波器组和FFT两个主要模块的FPGA实现方法进行了详细阐述。基于该设计方法进行了4路、8路和16路信道分路应用的FPGA硬件设计,给出了硬件占用资源情况和误码测试结果,从而证明该设计方法的可实现性。
In this paper,a design method of digital reconfigurable channel-separation is proposed. It is a design of serial configuration for polyphase array-FFT algorithm,in which the polyphase filter banks and FFT stage number are reconfigurable flexibly according to the channel number. Even up to hundreds of channels are configured. The paper presents in detail the implementation of the polyphase filter banks and FFT,two main modules involved in the design methods of digital reconfigurable channel-separation. Finally,the paper realizes 4-,8-,16- channel FPGA design with this design method. In addition,the hardware resource occupation and BER are presented,to prove the feasibility of this design method.
出处
《无线电工程》
2013年第12期25-28,共4页
Radio Engineering
