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5/3提升小波的FPGA动态RAM结构设计及其应用 被引量:3

Architecture Design of 5/3 Lifting Wavelet in FPGA with Dynamic RAMs and its Applications
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摘要 为了改善高分辨率TDICCD成像系统图像数据的高速传输特性,设计了FPGA内部实现5/3提升小波的动态RAM结构。该结构通过循环利用同一RAM资源进行图像数据的同时读写,解决了5/3提升小波在FPGA实现过程中的RAM不足问题,提高了RAM资源利用的有效性。试验表明,5/3提升小波在FPGA内部的动态RAM实现过程,具有实时性高、可靠性好、占用资源较小等优点。该方法在图像预压缩、图像去噪、图像实时传输等方面有重要的意义。5/3提升小波在FPGA中的动态实现,完成了5行数据存储的提升小波处理过程,增强了星上实时数据的处理能力,为后续程序的开发奠定了基础。 In order to improve the transmission performances of the high speed image transmission data in TDICCD imaging system, it designed the new structure with dynamic RAMs for designing 5/3 lifting wavelets in FPGA. It solved the problem that the RAMs in FPGA were not adequate in some applications by using the same RAM in loops and reading-or-writing, which improved the ability of the RAM used efficiency. The simulation results also indicated that the new structure was better at the aspects of high speed, high reliability, low resource used ratio. The structure could be used in image pre-compress, image de-noise, image transmission and other areas. The new structure of the 5/3 lifting wavelets implementation in FPGA, within 5 lines image storage finishing the processing, enhanced the processing ability of the image data in aero-space camera. It created a new way of data real-time process in space.
出处 《液晶与显示》 CAS CSCD 北大核心 2013年第6期927-932,共6页 Chinese Journal of Liquid Crystals and Displays
关键词 动态RAM 5 3提升小波 FPGA 时间延迟积分CCD dynamic RAM 5/3 lifting wavelet FPGA TDICCD
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