摘要
针对当前可逆比较器设计方案缺乏可扩展性的问题,提出了基于新型可逆门的具有可扩展性的可逆比较器可逆逻辑电路设计方案.该方案根据二进制数比较的特点采用递归思想将电路分解为2种新型可逆门,对分解出的每一个可逆门进行可逆逻辑综合,再将这2种可逆门级联成可逆比较器.给出了设计方案中每一步的逻辑演算,利用编码的思想进行带无关项的可逆逻辑综合,最终给出了具体的可逆比较器的综合方案.同时,以可逆比较器作为元器件给出了败者树排序电路,将排序的时间复杂度降低到Θ(n).
The design proposal for an extensible reversible comparator based on a novel reversible gate is presented to solve the problem that the previous scheme is not extensible. Using the method of recursion, the circuit is decomposed to two kinds of novel reversible gates according to the features of the binary number comparison. And each reversible gate is synthesized with reversible logic. The re- versible comparator is realized by cascading these reversible gates. The logical expression of every step is given; the theory of encoding is used to solve logic synthesis with ＂do not care＂ set; the detailed scheme for synthesizing reversible comparator is provided. Tournament sort circuit based on reversible comparator is presented, and the asymptotic time complexity of the circuit is decreased to ~9（n）.
出处
《东南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2014年第1期39-44,共6页
Journal of Southeast University：Natural Science Edition
基金
国家自然科学基金资助项目(61170321)
高等学校博士学科点专项科研基金资助项目(20110092110024)
关键词
可逆比较器
新型可逆门
递归
reversible comparator
novel reversible gate
recursion
