摘要
介绍了常用的水平垂直冗余校验码——(7×7)奇偶校验编码解码逻辑电路的EDA设计,用VHDL语言对(7×7)奇偶校验编码器和解码器进行描述,用Quartus II软件进行仿真测试.从仿真结果看,电路完全符合要求,可以烧写成芯片.
This paper introduces the design of logic circuit for （7 ＆#215; 7） parity generators and check-ers with EDA .It is a Longitudinal-Vertical Redundancy Check and is often applied in data trans-mission .The （7 ＆#215; 7） parity generators and checkers are simply described with VHDL language , and are simulated it with the software of Quartus II .The simulation results show that it can meet the requirements and can load chip .
出处
《山东理工大学学报（自然科学版）》
CAS
2014年第1期58-64,共7页
Journal of Shandong University of Technology:Natural Science Edition
