期刊文献+

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits 被引量:3

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits
原文传递
导出
摘要 Through-silicon-via(TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of threedimensional integrated circuits(3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely,driver sizing and via shielding, and the SPICE results show 241 mV and 379 mV reductions in the peak noise voltage,respectively. Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第3期591-596,共6页 中国物理B(英文版)
基金 Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
关键词 三维集成电路 串扰噪声 噪声模型 优化设计 通孔 TSV 信号完整性 three-dimensional integrated circuits, through-silicon-via crosstalk, driver sizing, via shielding
  • 相关文献

参考文献22

  • 1Pavlidis V F and Friedman E G 2009 Three-dimensional Integrated Circuit Design (San Mateo: Morgan Kaufmann) p.123.
  • 2Xie Y,Cong J and Sapatnekar S 2009 Three Dimensional IC: Design,CAD,and Architecture (New York: Springer) p.59.
  • 3Qian L B,Zhu Z M and Yang Y T 2011 Chin.Phys.B 20 108401.
  • 4Zhu Z M,Zuo P and Yang Y T 2011 Acta Phys.Sin.60 118001 (in Chinese).
  • 5Kim D H,Mukhopadhyay S and Lim S K 2011 IEEE Trans.Components,Packaging,and Manufacturing Technology 1 168.
  • 6Xu C,Suaya R and Banerjee K 2011 IEEE Trans.Electron.Devices 58 4024.
  • 7Song T G,Liu C,Peng Y R and Kim J H 2013 ACM/IEEE International Conference on Computer-Aided Design,June 1–7,2013 Austin,USA,p.1.
  • 8Pak J S,Ryu C H and Kim J H International Conference on Electronic Material and Packaging,November 19–22,2007 Daejeon,Korea,p.1.
  • 9Sun X,Zhu Y H,Ma S L and Miao M IEEE Electronics Packing Technology Conference,December 7–9,2011 Singapore,p.171.
  • 10Engin A E and Narasimhan S R 2013 IEEE Trans.Electromagnetic Compatibility 55 149.

同被引文献26

引证文献3

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部