摘要
逻辑功效法延时估算是由Sutherland I E提出的,可以在设计初期快速估算逻辑门和逻辑电路的延时,减小逻辑电路设计的难度。但是,随着深亚微米CMOS工艺的普及,短沟道效应开始影响经典逻辑功效法的正确性。为了提高逻辑功效法估算精度,提出一种考虑速度饱和效应的改进方法,该方法主要分两步:首先,考虑反相器PMOS与NMOS宽之比,精确估算反相器的延时,并归一化;然后,基于反相器的延时和速度饱和的影响,估算逻辑门的延时。仿真模型采用了美国亚利桑那州立大学的PTM 32nm、65nm、90nm和130nm的模型,45nm采用了北卡罗来纳州立大学的FreePDK的模型,结合hspice仿真。经实验数据对比,该方法对与非门延时的估算精度提高约10%。
Abstract：The logical effect delay estimation method, proposed by Sutherland I E,can quickly estimate the delay of the logic gates and logic circuits and reduce the diffieulty of logical circuits design at the beginning of design. With CMOS technology entering deep sub-micron, however, short channel effect has begun to affect the eorrectness of the method of classical logic effort. In order to improve the accuracy of logical effort estimation, the paper proposes an improvement method of logical effort based on the veloeity saturation. This method contains two main steps. Firstly, the width ratio of PMOS and NMOS in inverter is considered to precisely estimate the inverter delay, which is normalized. Secondly, logical gate delay is estimated based on inverter delay and velocity saturation. In hspice simulation, 32nm.65nm.90nm and 130nm from Arizona State University PTM （Predictive Technology Model）, and 45nm from North Carolina State University FreePDK are used. Comparative experiment demonstrates that our method improves the accuracy of the NAND gates delay estimation, approximately by 10%.
出处
《计算机工程与科学》
CSCD
北大核心
2014年第4期589-595,共7页
Computer Engineering & Science
关键词
逻辑功效
延时估算
速度饱和
深亚微米
logic effort
delay estimation
velocity saturation
deep sub-micron
