摘要
该设计的DAC为芯片内甄别器提供了一个可调的阈值,要求具有较高的精度,较低的功耗。基于chartered 0.35μm工艺,采用Spectre进行了仿真设计,非线性误差DNL<0.025 LSB,INL<0.17LSB,功耗低于3 mW。文章描述了R-2R型DAC的电路结构,主要介绍了电阻网络,抗单粒子翻转的DICE锁存器等的设计。最后给出了版图和后仿结果,满足设计的要求。
The DAC is used to provide an adjustable threshold voltage for a discriminator of chip ,the objective is high accuracy and low power .Based on the chartered 0.35μm process,designed and simulated by Spectre ,as a result with nonlinearity error of DNL 〈0.025LSB and INL〈0.17LSB , power under 3 mW.The paper pres-ents the architecture of R -2R Ladder DAC,mainly R-2R ladder topology and DICE latch in details .At last , the layout has been designed and the simulation results have certified in achieving the objective .
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2014年第2期134-137,151,共5页
Nuclear Electronics & Detection Technology
