摘要
传统的雷达信号处理系统的设计方法是针对特定应用的 ,因此系统的通用性差 ,而具有超级计算机体系结构的通用高速实时雷达信号处理系统有望解决这一问题。该系统的关键部件为担负具体计算任务的处理结点。首先提出了一种新型的、由 5片ADSP - 2 10 6x构成的多DSP并行计算结构。它具有运算能力强、I/O带宽大、通信手段多样、能灵活地改变拓扑结构、可扩展、通用性强等特点。并且以此并行计算结构为核心设计实现了通用高速实时雷达信号处理系统的处理结点。
The flexibility of conventional radar signal processing systems is highly limited because they are designed for their specific applications. For this problem, a general-purpose highspeed radar signal processing system based on parallel computer architecture may be a hopeful solution. One of the key components in such a system is the processing node which is chiefly responsible for the computation-intensive tasks. In this paper, a new multi-DSP parallel computing architecture including 5 ADSP-2106x chips is first presented. This architecture has many promising characteristics such as strong computational capability, broad I/O bandwidth, various communicating methods, topology flexibility, and good scalability. Then, using this architecture as the hardware core, a scheme of the processing node is developed.
出处
《系统工程与电子技术》
EI
CSCD
北大核心
2001年第3期19-22,共4页
Systems Engineering and Electronics
