摘要
分布式Viterbi译码器是一种物理分散、逻辑统一的译码器。它在多个现场可编程阵列（FPGA）上实现各功能模块，以充分利用各FPGA的容裕量，达到系统资源分配的平衡。通过一个大规模设计中分布式Viterbi译码器实例的剖析，说明分布式结构设计的特点及实现技术。这里给出的Viterbi译码器实例对其他分布式FPGA器件的设计也有较高的参考价值。
Distributed Viterbi decoder is physically apart, logically binding. By implementing the functional modules on diverse FPGAs, it utilized the resource on each FPGA to the most extent, and equalized the resource distribution among all FPGAs. This paper presented an example of distributed Viterbi decoder in a complex design, and introduced the features of the realization. Meanwhile, the design methodology of this distributed decoder can offer a good reference for other FPGA designs with distributed structure.
出处
《通信技术》
2001年第4期32-34,共3页
Communications Technology
基金
国家863资助项目(编号863-317-03-01-07-99)。
