摘要
文章以Quartus Ⅱ为软件平台,介绍数字逻辑电路的层次化设计方法,并充分利用Quartus Ⅱ的原理图设计模式以及硬件描述语言VHDL实现对各种数字逻辑电路的功能仿真和时序仿真。使学生逐步掌握现代数字系统设计的实验方法,提高其设计水平和效率,同时进一步提高学生自身的综合素质。
In this paper we introduced the hierarchical design method of digital logic circuit which with Quartus Ⅱ as software platform, and makes full use of Quartus Ⅱ schematic design mode and hardware description language VHDL to realize functional simulation and timing simulation of various digital logic circuits. Students will gradually master the experimental methods of modern digital system design, improve their design level and efficiency, and further improve the overall quality of students.
作者
王来花
Wang Laihua(School of Software,Qufu normal University,Shandong 273165)
出处
《电子技术（上海）》
2018年第11期89-90,86,共3页
Electronic Technology
基金
曲阜师范大学虚拟仿真实验项目(SJ201715)
