摘要
阐述了6 500 V4H-SiC结势垒肖特基(JBS)二极管的设计、仿真和制备过程,并对流片结果进行了测试,分析了测试结果与仿真结果差异的原因。通过仿真对比分析了漂移区厚度、掺杂浓度、有源区p+区和场限环终端参数对器件电学特性的影响,数值模拟优化了器件元胞和终端结构的漂移区、有源区和场限环的结构参数。根据模拟结果,4H-SiC漂移区掺杂浓度为1.08×10^15 cm^-3、厚度为60μm,采用经过优化的70个场限环终端结构,通过完整的工艺流程,完成6 500 V4H-SiC JBS的制备。测试结果显示,室温下当6 500 V4H-SiC JBS正向导通电流密度达到3.53×10^5 A/m^2时,正向压降为4 V,器件的反向击穿电压约为8 000 V。
The design,simulation and fabrication process of the 6 500 V4 H-SiC junction barrier Schottky(JBS)diodes were presented.The performances of the fabricated diodes were tested,and the reasons of the difference between the test results and the simulation results were analyzed.The effects of the drift region thickness,doping concentration,active region p+region and field limiting ring termination parameters on the electrical properties of the devices were contrastively analyzed by the simulation.The structure parameters of the drift region,active region and field limiting ring of the device cell and termination structure were optimized through the numerical simulation.According to the simulation results,the 4 H-SiC drift region has a doping concentration of 1.08×10^15 cm^-3 and a thickness of 60μm.Besides,by using the optimized termination structure with 70 field limiting rings,the 6 500 V4 H-SiC JBS was fabricated through the complete process flow.The test results show that the forward voltage drop is 4 V and the reverse breakdown voltage is about 8 000 V when the forward conducting current density of the 6 500 V4 H-SiC JBS is 3.53×105 A/m2 at room temperature.
作者
李嘉琳
桑玲
郑柳
田丽欣
张文婷
Li Jialin;Sang Ling;Zheng Liu;Tian Lixin;Zhang Wenting(Department of Power Semiconductors,Global Energy Internet Research Institute Ltd.,Beijing 102209,China;State Key Laboratory of Advanced Power Transmission Technology,Beijing 102209,China)
出处
《微纳电子技术》
北大核心
2019年第2期95-100,共6页
Micronanoelectronic Technology
基金
国家电网公司总部科技项目(5455GB180001)
