摘要
在ASIC设计中,越来越多地采用了SoC（systems-on-a-chip）方法,同时也因为采用各种IP核和嵌入存储器,给芯片的设计和测试带来了复杂性,特别是在ATPG中这些单元对故障覆盖率有较大的影响.现在已经有一些测试嵌入存储器本身的方法,但这些方法一般不考虑嵌入存储器对周围逻辑可测性的影响.在分析了嵌入存储器对ATPG的影响后,提出了消除这些影响的RTL级的DFT方法,这种方法得到了实验的检验.
In ASIC design, SoC (systems-on-a-chip) has been used more and more frequently. Meantime chip design and test become more complex due to the integration of embedded IP cores and embedded memories. Especially, in ATPG these units have significant influence on fault coverage. Some methods have been developed in the testing memory, but generally they do not consider the influence of embedded memory on the testability of surrounding logic. After analyzing the influence of embedded memory on ATPG, an RTL level DFT method is proposed to eliminate the problem. The effectiveness of the method has been proved by experiment.
出处
《计算机研究与发展》
EI
CSCD
北大核心
2002年第6期763-766,共4页
Journal of Computer Research and Development
关键词
SOC设计
嵌入存储器
ATPG
系统级芯片
可测性设计
systems-on-a-chip (SoC), automatic test pattern generation (ATPG), design for testability (DFT) , embedded memory
