摘要
研究DPA攻击方法以及相应的电路级防护技术,提出在FPGA(现场可编程门阵列)上实现WDDL的设计方法以及适用于FPGA的对称布线技术,随后在FPGA平台上实现一个4位加法器并进行功耗分析。实验结果表明,WDDL电路的功耗波动比普通电路有较明显的下降。WDDL结构以一定的芯片面积为代价,可有效降低FPGA功耗与数据的相关性,具有较好的抗DPA(差分功耗分析)攻击性能。
The authors studied the DPA attack method and circuit level protection technology, and introduced a security circuit WDDL on FPGA and a new symmetrical routing technology. A 4-bit WDDL adder on FPGA （field programmable gate array） platform was implemented and the power consumption of the circuit was analyzed. The results show that power consumption of WDDL decreases obviously than that of the traditional circuit and WDDL circuit can reduce the correlation of power consumption and data effectively. WDDL is proved to have better anti DPA （differential power analysis） attack ability at the cost of chin size.
出处
《北京大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2014年第4期652-656,共5页
Acta Scientiarum Naturalium Universitatis Pekinensis
