期刊文献+

多核DSP实时图像处理平台设计与实现 被引量:7

Design and Implementation of Image Processing Platform with Multi-core DSP
下载PDF
导出
摘要 为了实现对高帧率、高分辨率图像的智能化实时处理,要求图像处理系统具有较高的数据传输带宽和数据处理能力。采用多核DSP作为核心处理器来解决目前图像采集平台面临的数据传输瓶颈和处理瓶颈,利用FPGA硬件化并行处理的特性完成多路视频的预处理,设计了高速串口Rapid Io通信接口实现视频的实时传输,对DSP的多核调度特性进行分析,保证处理的实时性,并采用相关算法验证系统的性能。 In order to achieve intelligent real- time processing of the image with high frame rate or high resolution,the image processing system has been required to have higher data transmission bandwidth and data processing capacity. Multi- core DSP is used as the core processor to solve the data transmission and processing bottleneck which the current image acquisition platform facing. The characteristics of FPGA' s hardware parallel processing are made use of to complete the preprocessing of multi- channel vedio. The communication interface of high- speed serial Rapid Io is designed to realize real- time transmission of the video. The multi- core scheduling characteristics carry on being analysed to ensure the real- time processing,and test the system's performance based on related algorithm.
出处 《航空计算技术》 2015年第1期131-134,共4页 Aeronautical Computing Technique
基金 航空科学基金项目资助(2014ZC31004)
关键词 实时处理 硬件化并行 高速串口 多核调度 real-time processing hardware parallel high-speed serial multi-core scheduling
  • 相关文献

参考文献6

  • 1Taxas Instruments Inc. KeyStone Architecture Multicore Nav- igator User Guide [ EB/OL]. http://www, ti. com/lit/ug/ sprugr9d/sprugr9d, pdf,2011 - 12.
  • 2张娟娟,陈迪平,柴小丽.VxWorks下RapidIO互连系统的实现[J].计算机工程,2011,37(3):236-237. 被引量:8
  • 3Taxas Instruments Corp. UCD9222 Data Sheet [ EB/OL]. ht- tp ://www. ti. com/product/ucd9222, pdf,2012 -02.
  • 4Wu Hao,Xiao Ji-yang,Fan Hong-qi,et al. TMS320C6678 Multi- core DSP Communication on Method Between Nuclear [ J ]. Eectronic Technology,2012,38 (9) : 2 - 3.
  • 5龚向坚,邹腊梅,胡义香.基于OpenMP的多核系统并行程序设计方法研究[J].南华大学学报(自然科学版),2013,27(1):64-68. 被引量:9
  • 6Taxas Instruments. OpenMP Programming for Keystone Mul- ticore Processors[ EB/OL]. http ://www. ti. com,2012.

二级参考文献15

  • 1张平,李清宝,赵荣彩.OpenMP并行程序的编译器优化[J].计算机工程,2006,32(24):37-40. 被引量:13
  • 2Tundra Semiconductor Corporation.Tsi578TM Serial RapidIO Switch User Mannal[EB/OL].(2006-10-11).http://www.tundra.com.
  • 3RapidIO Trade Association.RapidIO Interconnect Specification,Rev.1.3[EB/OL].(2005-06-07).http://www.rapidio.org.
  • 4FuIler S.RapidIO:The Embedded System Interconnect[M].[S.1.]:John Wiley & Sons Ltd..2005.
  • 5Freescale Semiconductor.MPC8641D Integrated Host Processor Family Reference Manual[EB/OL].(2008-07-28).http://www.freescale.com.
  • 6Olukotun K, Nayfeh B A, Hammond L, et al. The case for a single-chipmultiprocessor [ J ]. ACM SIGPLAN No- tices. , 1996,31 (9) :2-11.
  • 7Cesare Ferri. SoC-TM: IntegratedHW/SWSupportfor trans- actiona memory programmingon embedded MPSoCs [ J ]. Published by ACM 2011:39-48.
  • 8Feng H, Li E, Chen Y, et al. Parallelization and charac- terization of SIFT on multi-core systems [ C ]. IEEE Inter- national Symposium on Workload Characterization,2008. Seattle, USA, 2008.
  • 9Tam D, Azimi R, Stumm M. Thread clustering: sharing-a- ware scheduling on smp-cmp-smt multiprocessors [ C ]// The 2nd ACM SiGOPS/EuroSys European Conference on Computer Systems. Lisbon, Portugal,2007:47-58.
  • 10Lee R, Ding X, Chen F, et al. MCC-DB: minimizing cache conflicts in multi-core processors for databases [ J]. Proceedings of the VLDB Endowment. 2009,2( 1 ) : 373 -384.

共引文献15

同被引文献34

引证文献7

二级引证文献22

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部