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用于DVFS片上系统的全数字SARDLL设计 被引量：1

Design of All Digital SARDLL for DVFS System-on-Chip
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摘要 针对动态电压/频率调整系统芯片中时钟同步问题,设计一个具有宽工作频率范围和固定锁定周期的快速锁定全数字逐次逼近延时锁定环,采用改进的可复位数字控制延时线方法,在减小面积和提高最高工作频率的同时,有效地解决传统全数字逐次逼近延时锁定环的谐波锁定和零延时陷阱问题。整个延时锁定环采用TSMC-65 nm CM OS工艺标准单元库实现,仿真结果表明,在典型工艺角和25℃情况下,工作频率范围为250 M Hz^2 GHz,锁定时间为固定的18个输入时钟周期,当电源电压为1.2 V、输入时钟频率为2 GHz时,功耗为0.4 m W。 An all digital fast-locking Successive Approximation Register-controlled Delay-Locked Loop（ SARDLL） with w ide-range operating frequency and constant acquisition cycles is presented for the clock synchronization of Dynamic Voltage / Frequency Scaling（ DVFS） System-on-Chip（ So C）. The improved resettable Digitally Controlled Delay Line（ DCDL） scheme is adopted to effectively solve the harmonic lock problem and zero-delay problem of the conventional all digital SARDLL,meanw hile reduces the hardw are overhead and increases the maximum operating frequency. The presented all digital SARDLL is implemented using the TSM C-65 nm CM OS standard cell library. Based on the typical corner and25℃,the post-layout simulation results show that the operating frequency range is from 250 M Hz to 2 GHz,the lock time is18 cycles of the input clock signal and the pow er consumption is 0. 4 m W at 2 GHz and 1. 2 V supply voltage.
作者 徐太龙 薛峰 高先和 蔡志匡 韩少宇 胡学友 陈军宁
机构地区 合肥学院电子信息与电气工程系 安徽三联学院电子电气工程学院 南京邮电大学电子科学与工程学院 安徽大学电子信息工程学院
出处 《计算机工程》 CAS CSCD 北大核心 2015年第4期273-276,283,共5页 Computer Engineering
基金 安徽省教育厅自然科学研究基金资助重点项目(KJ2014A211) 合肥学院重点建设学科基金资助项目(2014xk06)
关键词 动态电压/频率调整 延时锁定环 时钟偏差 片上系统 锁定时间 谐波锁定 零延时陷阱 Dynamic Voltage/Frequency Scaling（DVFS） Delay-Locked Loop（DLL） clock skew System-on-Chip（So C） lock time harmonic lock zero-delay trap
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献15

  • 1Yao C Y,Ho Y H,Chiu Y Y,et al. Designing a SAR- based All-digital Delay-locked Loop with Constant Acquisition Cycles Using a Resettable Delay Line [ J ] IEEE Transactions on Very Large Scale Integration Systems ,2014,22 ( 9 ) : 1-8.
  • 2徐太龙,薛峰,蔡志匡,郑长勇.快速全数字逐次逼近寄存器延时锁定环的设计[J].计算机工程,2014,40(4):262-268. 被引量：1
  • 3徐太龙,陈军宁,孟坚,徐超,柯导明.全数字延时锁定环的研究进展[J].小型微型计算机系统,2013,34(6):1371-1374. 被引量：2
  • 4DehngGuang-Kaai, Hsu June-Ming, Yang Ching-Yuan, et al. Clock-deskew Buffer Using a SAR-controlled Delay-locked Loop [ J ]. IEEE Journal of Solid-state Circuits ,2000,35 ( 8 ) : 1128-1136.
  • 5Flynn D. Intelligent Energy Management: An SoC Design Based on ARM926EJ-S [ C ]//Proceedings of the 15th Hot Chips Conference. Berlin, Germany: Springer, 2003.
  • 6Chen Weicheng,Yang Rong-Jyi, Yao Chia-Yu, et al. A Wide-range All-digital Delay-locked Loop Using Fast- lock Variable SAR Algorithm [ C ]//Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems. Washington D. C. , USA: IEEE Press ,2012:338-342.
  • 7Yao Chia-Yu, Ho Yung-Hsiang. A Fast-locking Wide- range All-digital Delay-locked Loop with a Starting SAR-bit Prediction Mechanism [ C]//Proceedings of International Symposium on VLSI Design, Automation, and Test. Washington D. C., USA: IEEE Press,2013: 1-4.
  • 8Chung Ching-Che, Chang Chia-Lin. A Wide-range All- digital Delay-locked Loop in 65 nm CMOS Technology[ C]//Proceedings of International Sympo- sium on VLSI Design, Automation, and Test. Washington D. C. , USA : IEEE Press, 2010 : 66-69.
  • 9Chen Yougang, Tsao H W, Hwang C S. A Fast-locking All-digital Deskew Buffer with Duty-cycle Correction[J]. IEEE Transactions on Very Large Scale Integration Systems, 2013,21 ( 2 ) : 270-279.
  • 10Park J H,Jung D H, Ryu K, et al. ADDLL for Clock- deskew Buffer in High-performance SoCs [ J ]. IEEE Transactions on Very Large Scale Integration Systems, 2013,21(7) :1368-1373.

二级参考文献25

  • 1陆平,郑增钰,任俊彦.延迟锁定环(DLL)及其应用[J].固体电子学研究与进展,2005,25(1):81-88. 被引量：4
  • 2上官利青,刘伯安.用于频率综合器的延迟锁相环的设计[J].微电子学,2007,37(1):72-75. 被引量：4
  • 3任敏华,张伟,徐国强.数字延迟锁定环设计技术研究[J].计算机工程,2007,33(17):262-264. 被引量：3
  • 4Yang R J, Liu S I. A 40-550 MHz Harmonic-free All-digital Delay-locked Loop Using a Variable SAR Algorithm[J]. IEEE Journal of Solid-state Circuits, 2007, 42(2): 361-373.
  • 5Moorthi S, Meganathan D, Krishna N, et al. A Novel 14- 170 MHz All Digital Delay Locked Loop with Ultra Fast Locking for SoC Applications[C]//Procl of Conference on Recent Advances in Intelligent Computational Systems. [S. 1.]: IEEE Press, 2011: 76-80.
  • 6Fang J, Luk W S, Zhao W. True Worst-case Clock Skew Estimation Under Process Variations Using Affine Arithmetic[J]. Chinese Journal of Electronics, 2007, 16(4): 631-636.
  • 7Chen Y G, Tsao H W, Hwang C S. A Fast-locking All-digital Deskew Buffer with Duty-cycle Correction[J]. IEEE Transactions on Very Large Scale Integration Systems, 2012, 21(2): 1-11.
  • 8Xanthopoulos T. Clocking in Modem VLSI Systems (Integrated Circuits and Systems)[M]. New York, USA: Springer, 2009.
  • 9Lee H W, Kim K H, Choi Y K, et al. A 1.6 V 1.4 Gbp/s/pin Consumer DRAM with Self-dynamic Voltage Scaling Technique in 44 nm CMOS Technology[J]. IEEE Journal of Solid-state Circuit, 2012, 47(1): 131-140.
  • 10Moon J, Lee H Y. A Dual-loop Delay Locked Loop with Multi Digital Delay Lines for GHz DRAMs[C]//Proc. of IEEE International Symposium on Circuits and Systems. [S. 1.]: IEEE Press, 2011: 313-316.

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计算机工程
2015年 第4期

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