摘要
随着数字技术的不断发展,数字滤波在数字信号处理领域占据不可替代的地位。文章首先介绍了数字滤波器的理论,DSP器件在高速和实时系统中的应用有一定局限性的问题提出了基于FPGA消除基带传输系统码间干扰的实现方案。该方案设计了一个33阶的具有对称转置结构的平方根升余弦滚降(SRRC)滤波器。首先通过MATLAB对滤波器系数进行了提取,并对浮点型系数进行量化和CSD编码形成定点型系数,使之能够在FPGA中运行。利用硬件描述语言Verilog对所设计的滤波器各功能模块进行设计。最后釆用仿真综合软件Modelsim和Quartus II对顶层模块进行综合与仿真。仿真后得到的滤波后数据波形图与Matlab下理论性的滤波后数据波形图基本相吻合,证明了所设计的SRRC数字滤波器功能完全正确。
With the development of digital technology,digital filter occupys an irreplaceable position in signal processing field.This paper first introduces the theories of digital filter. Aiming at the problem that DSP device has certain limitations in the application of high speed and real-time system,an implementation method based on FPGA to eliminate inter-symbol interference in baseband transmission system is presented. A 33 order SRRC digital filter with symmetric transpose structure was designed by this method.Firstly,the filter coefficient was extracted by using Matlab.Then it was be quantized and CSD coded to be able to operate in FPGA.Secondly, Each function module of the filter was designed by using Hardware Description Language—Verilog.Finally,the top-level module was synthesized and simulated with Modelsim and Quartus II.The data waveform following filtering after simulation was basically consistent with the theoretical filtering data waveform under Matlab. It indicated that the function of the designed SRRC digital filter is exactly right.
出处
《电子技术（上海）》
2015年第4期78-84,77,共8页
Electronic Technology
关键词
平方根升余弦滚降滤波器
仿真
硬件描述语言
冲击响应系数
移位相加方法
乘法器法
square-root raised cosine roll-off digital filter
simulation
hardware description language
impulse response coefficient
shifting and adding method
multiplier method
