摘要
智能变电站过程层网络SMV报文组网的传输方式已成为一种趋势。SMV报文组网的传输方式具有信息共享便捷的优势,但是SMV报文在网络交换设备交换机中传输的延时具有不确定性,这样就需要可靠的时钟源来进行同步,而且合并单元需要具备一定的守时能力。为了使SMV报文组网的传输方式不依赖外部时钟源,尝试对交换机进行改进,给出了一种基于FPGA的过程层SMV报文传输延时可测的交换机架构,提出了一种利用IEC 61850-9-2帧结构中Reserved字段测量并记录传输延时的方案。经过验证,该架构和方案可以准确地测量SMV报文在网络中传输的延时。
Constructing SMV network of intelligent substation process layer with switches has been becoming a fashion. This structure is convenient to share information among multiple devices, but it leads to uncertainty and indeterminacy in terms of time delay when transmitting in the network. This drawback requires a reliable time resource to realize synchronization, and the merging unit should have the ability of time keeping to a certain degree. To solve these problems, this paper gives a structure of switch based on FPGA aiming to measure the time delay of SMV packets transmission, and proposes a scheme of measuring and storing the time delay using the reserved bytes in IEC 61850-9-2 frame. FPGA realization and experiments justify the proposed structure and scheme of the time delay measurement.
出处
《电力系统保护与控制》
EI
CSCD
北大核心
2015年第10期111-115,共5页
Power System Protection and Control
