期刊文献+

封装键合点对IGBT UIS失效的影响研究 被引量:3

Influence of bonding location on IGBT's failure under UIS condition
下载PDF
导出
摘要 为了解决绝缘栅双极型晶体管在实际应用当中的典型关断失效问题,对其在电感无钳位开关条件下的电压应力、电流应力、雪崩能力以及失效模式进行了研究。基于电感无钳位开关测试电路,着重探讨了UIS条件下IGBT的击穿机理。封装打线时将铝线分别键合于多个IGBT芯片发射极的不同部位,并基于自主搭建的测试平台,对该批初步封装的IGBT芯片进行了电感无钳位开关条件下的应力测试。最后提出了封装改进建议,避免封装键合点对于IGBT UIS失效的影响。实验结果表明:封装焊线在IGBT发射极金属所引入的横向电阻会导致IGBT芯片的并联元胞等效电阻不均匀,并使电流更易集中于封装键合点附近,最终导致IGBT芯片在UIS条件下的失效点均位于铝线键合点附近。 Aiming at solving the turn-off failure of the IGBT device in application, the voltage stress, current stress, avalanche energy endurance and failure pattern of IGBT was studied under unclamped inductive switching (UIS) condition. Based on the UIS test circuit, the failure mechanism was discussed in detail. Aluminum wires were bonded on different location of IGBT bare chips separately during packaging. The UIS experiment was carried out on these chips based on self-assembled experimental platform. Advice on packaging improvement was pro- posed to avoid the influence of wire bonding on UIS failure. The experimental results indicate that the wire bonding introduced lateral resist- ance on the emitter metal pad of IGBT would cause the nonuniformity of resistance in paralleled IGBT cells and thus result in the current constriction in ceils near bonding spots till failure. Therefore, the failure spots on the IGBT chip stick to the bonding spots.
出处 《机电工程》 CAS 2015年第5期707-711,共5页 Journal of Mechanical & Electrical Engineering
基金 国家电网公司科技资助项目(SGRI-WD-71-14-005) 浙江省教育厅科研资助项目(Y201329864) 中央高校基本科研业务费专项资金资助项目(2014FZA4014)
关键词 绝缘栅双极型晶体管 UIS 失效分析 insulated gate bipolar transistor (IGBT) unclamped inductive switching (UIS) failure analysis
  • 相关文献

参考文献5

二级参考文献76

  • 1王正仕,吴益良,向群,陈辉明.IGBT的过流保护[J].电力电子技术,1996,30(3):70-73. 被引量:6
  • 2杨斌文,胡浩,张建.IGBT的有关保护问题[J].电气开关,2006,44(6):7-9. 被引量:5
  • 3陈振伟,陈辉明,王正仕,刘磊.一种新型单电源IGBT驱动电路[J].机电工程,2007,24(9):33-35. 被引量:2
  • 4BISWAS S K, BASAKB, RAJASHEKARA KS. A Modular Gate Drive Circuit For Insulated Gate Bipolar Transistors [ C]// Conference Record of IEEE IAS 1991. Dearborn: [ s. n. ] ,1991:1490 - 1496.
  • 5SHIMIZU Y, NAKANO Y, KONO Y, et al. A High performance intelligent IGBT with overcurrent protection [ C ]// Proceedings of ISPSD 1994 : [ s. n. ] , 1994 :37 - 41.
  • 6Daniel D, Andrej V. Analysis of the electrical and thermal prop- erties of power DMOS devices during UIS supported by 2-D pro- cess and device simulation. The Fifth International Conferenceon Advanced Semiconductor Device and Microsystems, 2004: 211.
  • 7Pawel I, Siemieniec R, R6sch M, et al. Experimental study and simulations on two different avalanche modes in trench power MOSFETs. IET Circuits Devices Syst, 2007, 1(5): 341.
  • 8Daniel D, Andrej V, Juraj M, et al. Evaluation of the rugged- ness of power DMOS transistor from electro-thermal simulation of UIS behavior. Solid-State Electron, 2008, 52:892.
  • 9Breglio G, Irace A, Napoli E, et al. Study of a failure mechanism during UIS switching of planar PTHGBT with current sense cell. Microelectron Reliab, 2007, 47:1756.
  • 10Lefranc P, Planson D, Morel H, et al. Analysis of the dynamic avalanche of punch through insulated gate bipolar transistor (PT- IGBT). Solid-State Electron, 2009, 53:944.

共引文献62

同被引文献16

引证文献3

二级引证文献17

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部