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传输线脉冲发生器研制及其对电路板抗静电放电干扰的测试 被引量:7

Development of Transmission Line Pulser and Its Immunity Test for Electrostatic Discharge on Printed Circuit Board
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摘要 为研究静电放电对电路板的干扰,利用传输线脉冲发生器提供激励脉冲,并配合测试探头,对电路板进行干扰测试,并以一单片机系统为测试对象进行干扰研究。首先,根据传输线脉冲生成原理,用同轴电缆、水银继电器及高压源设计和制作了1个传输线脉冲发生器,并将脉冲波的上升时间控制在1 ns以内;然后,分别用电场探头、磁场探头和注入探头建立了激励信号与被干扰对象之间的电场、磁场和传导耦合,通过试验观察了其耦合干扰信号,并研究了测试单片机系统的抗干扰特点。通过研究及测试得出:为保证传输线脉冲发生器的脉冲上升时间的要求,应选择快速继电器,控制好继电器与同轴电缆的连接以减少寄生参数的影响;用传输线脉冲发生器配合电场、磁场和注入探头进行测试,可以探查电路板的局部抗干扰薄弱环节;测试的单片机系统的抗干扰特点体现在:其局部区域对磁场干扰较敏感,晶振引脚和复位引脚对直接注入干扰更敏感。 In order to study interference of electrostatic discharge on printed circuit board(PCB), we used a transmission line pulser(TLP) to provide exciting pulses and added it with testing probes to do interference test. We took a single-chip microcontroller system as a test object to study the inference. Firstly, according to the principle of generating a TLP, we designed a TLP by using coaxial cable, mercury relay and high voltage source, and controlled its rising time of pulse within 1 ns. Then, we established the electric field coupling, magnetic field coupling and conduction coupling from excit- ing signal to interfering object by using electric field probes, magnetic field probes, and injection probes, respectively. Lastly, we observed the interfering signals by experiments, and studied the interference features of single-chip microcon- troller system. It is concluded that, in order to meet the requirements of rising time for TLP, we should choose a fast relay and control the connection of relay and coaxial cable to reduce effect of parasitic parameters. Weakness resisting to inter- ferences in local region of PCB can be detected by using TLP which is associated with electric field, magnetic field, and injection probes. Immunity features of the test single-chip microcontroller are that their certain regions are more sensitive to magnetic field interference, and their crystal oscillator pins and reset pins are more sensitive to direct injection interference.
出处 《高电压技术》 EI CAS CSCD 北大核心 2015年第5期1610-1617,共8页 High Voltage Engineering
基金 山东省自然科学基金(Y2008F31)~~
关键词 传输线脉冲发生器 静电放电 上升时间 印刷电路板 耦合 单片机 transmission line pulser electrostatic discharge rise time printed circuit board coupling single-chip microcontroller
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参考文献18

  • 1Smedes T. ESD testing of devices, ICs and systems[J]. Mieroelectron- its Reliability, 2009, 49(9/11): 941-945.
  • 2原青云,刘尚合,吴勇,武占成,杜祥民.静电放电抗扰度试验方法存在的问题及相关研究[J].军械工程学院学报,2008,20(4):58-62. 被引量:3
  • 3邓桃,吴广宁,周凯,吴建东.一种纳秒级高压脉冲发生器的研制[J].高压电器,2007,43(2):131-132. 被引量:8
  • 4Grand E, Gauthier R. TLP systems with combined 50 and 500-Ω impedance probes and kelvin probes[C]//Electrics Overstress / Electrostatic Discharge (EOS/ESD) Symposium. Las Vegas, USA: [s.n.], 2003: 1-10.
  • 5IEC 61000-4-2 Electromagnetic compatibility (EMC) part 4: testing and measurement techniques section 2: electrostatic discharge immun- ity tests[S], 2001.
  • 6Jayong K, Qing C, David P, et aL The repeatability of system level ESD test and relevant ESD generator parameters[C]//Proceedings of IEEE International symposium on EMC. Detroit, Michigan, USA: IEEE, 2008: 1-6.
  • 7Lin D, Pommerenke D, Barth J, et al. Metrology & methodology of system level ESD testing[C]//Electric Overstress/Electrostatic Dis- charge(EOS/ESD) Symposium. Reno, USA: [s.n.], 1998: 29-39.
  • 8Cao Y Q, Jotmsson D, Amdt B, et al. A TLP-based human metal model ESD-generator for device qualification according to IEC 61000-4-2[C] //Proceedings of Asia-Pacific Symposium on Electromagnetic Com- patibility. Beijing, China: [s.n.], 2010: 471-474.
  • 9Wolfgang S, Tilo B, Reinhold G, et al. Do ESD fails in systems corre- late with IC ESD robustness[J]. Microeleetronics Reliability, 2009, 49(9/11): 1079-1085.
  • 10曾传滨,李晶,王显泰,海潮和,韩郑生.传输线脉冲发生器电压探测中振荡问题的研究[J].半导体技术,2009,34(4):365-369. 被引量:1

二级参考文献85

  • 1郑小云.示波器探头对测量结果的影响分析[J].火控雷达技术,2006,35(4):43-45. 被引量:1
  • 2MIL-STD-883G-2006, Test Method Standard Microcircuits [S] .
  • 3MIL-STD-750E-2006, Test Method Standard Test Methods for Semiconductor Devices [S] .
  • 4JEDEC JESD22-A114-E-2006, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [S] .
  • 5JEDEC JESD22-A115-A-1997, Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [S] .
  • 6JEDEC JESD22-C101-A-2004, Field-Induced Charged- Device Model Test Method for Electrostatic-Discharge- Withstand Thresholds of Microelectronic Components [S] .
  • 7IEC 61000-4-2-2001 Electromagnetic Compatibility (EMC) -Part 4-2: Testing and Measurement Techniques-Electrostatic Discharge Immunity Test [S] .
  • 8GB/T17626.2-1998.电磁兼容试验和测量技术静电放电电抗扰度试验[S].
  • 9MALONEY T, KHURANA N. Transmission line pulsing techniques for circuit modeling of ESD phenomena [ J]. Proc EOS/ESD Symp. Minneapolis, USA, 1985, EOS-7 : 49-54.
  • 10CHEN T Y, KER M D. Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process [ J]. IEEE Trans on Semiconductor Manufacturing,2003,16(3):486-500.

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