摘要
为了实现可反馈式高速同步串行总线设计,提出基于FPGA使用硬件描述语言(HDL)和利用串行通信的本身电气特性设计出可反馈式电路,实现高可靠、高速率的同步串行总线通信方法。在工程应用中验证了其高速率和高可靠性的总线传输特性,为提高LRM(现场可更换单元)级之间总线速率提供参考。
In order to realize the design of highspeed synchronous serial bus,a method of designing the feedback type integrated circuit by hardware description language and electric characteristics of serial communication,and realizing highreliability and highspeed synchronous serial bus communication based on FPGA is proposed. The highspeed and highreliability bus transmission characteristics were verified in project application. It can provide an important reference for improving the speed of bus in LRU.
出处
《现代电子技术》
北大核心
2015年第12期139-142,共4页
Modern Electronics Technique
