摘要
为缩短SoC的测试时间并减少测试硬件开销,提出一种高性能SoC测试结构.通过重用存储控制逻辑作为测试接口,可以消除传统双向测试总线寄生的时间间隙,同时建立的流水化测试时序,避免了测试通道中引入的关键路径;针对功能和结构双重测试需求,复用片上总线系统作为测试访问机制结构并对其进行无损式改造,减少了测试访问的等待时长;同时构建的一种不依赖于目标核的测试环,维持了测试通道与扫描链之间的带宽平衡.实验结果表明,引入的测试结构使得测试时间缩短68%,面积开销下降36.1%,同时有效降低了对原始芯片性能的影响.
To reduce the testing time and decrease the testing overhead of hardware for SoC,a high-performance SoC test structure was presented.The structure could eliminate turnaround cycle existing in traditional bi-directional test bus by reusing memory controller as test interface,while it can avoid crucial path in test channel through establishing apipelined test sequence.Aiming at both functional and structural test requirements,the on-chip bus reused as TAM without the destructive modification could shorten the waiting cycles of test access.To balance the bandwidth between test paths and scan chains,a test wrapper independent of target core was integrated.Test results show that the approach shortens the testing time by 68%,and reduces the area overhead by 36.1%,which considerably mitigates the effects on the performance of the original chip.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2015年第5期500-505,共6页
Transactions of Beijing Institute of Technology
基金
国家"八六三"计划项目(2011AA120204)
航天创新计划项目(YY2011-012)
关键词
存储接口
测试访问机制
片上总线
测试环
memory interface
test access mechanism
on-chip bus
test wrapper
