摘要
针对电流调制式频率扫描绝对距离测量对信号采集的特点,应用FPGA逻辑功能与高速串行A/D转换芯片AD7812设计了一种高集成度的数据采集系统。该采集系统一方面满足与电流调制电路同步触发的要求,另一方面实现了采样频率严格一致与大数据的后台缓存目的,适合于测量系统对采样信号的后续处理。采集系统主要包括FPGA的A/D转换控制、软硬同步触发、FIFO高速缓存等模块,完成电流正负调制有效区干涉信号的多路准同步实时采集。运用FPGA内嵌的Nios软核与上位机的串行通讯功能,提取缓存的实验数据显示,验证了该采集系统的有效性与实用性。
In view of characteristics of the current modulation frequency scanning in absolute distance measurement signal acquisition,the data acquisition system with high level of integration was designed by using logic function of FPGA and high speed serial A / D conversion chip AD7812. On the one hand,the acquisition system meet the requirements of synchronized trigger with current modulation circuit,on the other hand,it realized the purposes of strict accordance with the sampling frequency and the big background for data caching. So,it is suitable for the measuring system subsequent processing of sampled signal. Acquisition system mainly included A / D conversion control of the FPGA,synchronous trigger between software and hardware and FIFO module,to complete the multi-channel synchronous real-time acquisition of interference signal that from effective area which has been current plus or minus modulation. Using the FPGA embedded Nios soft core and PC serial communication function to extract and display the experimental cache data,this paper verified the effectiveness and practical of the acquisition system.
出处
《仪表技术与传感器》
CSCD
北大核心
2015年第6期107-110,共4页
Instrument Technique and Sensor
基金
国家自然科学基金项目(51175154
51275157)
湖北省杰出青年人才基金项目010CDA088)
教育厅中青年项目(Q20101405
Q20101407)
湖北省科技厅项目(2010CDB03104)
关键词
绝对距离测量
同步触发
串行数据采集
FIFO
absolute distance measurement
synchronized trigger
serial data acquisition
FIFO
