摘要
PLC内部设置有众多的定时器,通常在工程应用中只使用了部分定时器。因此应用ARM-FPGA架构的PLC系统,设计FPGA定时器控制器的体系结构,1 ms作为基本定时单位,采用地址映射存储器顺序存储被PLC用户程序使用了的定时器的编号,只对被使用的定时器进行定时操作,提高了PLC的定时计数处理速度。阐述了定时器控制器的各功能模块的工作原理,以及与FPGA中央控制器的通信方式和通信的指令命令。经过仿真与测试,定时误差不大于0.1 ms,减少了PLC定时器执行定时操作的时间,达到精确定时的目的。
PLC is internally provided with numerous timers, and usually in engineering applications only uses a part of it.Using the PLC system of ARM-FPGA architecture, we designed the FPGA timer controller＇ s system structure.Taking 1ms as the basic timing unit, by using the memory of address mapping, we sequentially stored the timer number that be used by PLC user program, and only the timer that be used by PLC user program can be performed the timing operation, thus improved the processing speed of PLC timing.The working principle of each function module of the timer controller, and the communication mode and the communication command between the FPGA central controller and the timer controller were described.The simulation and testing shows that the timing error is within lms or less ,which reduces the time of PLC timer perform the timing operation and achieves the purpose of precise timing.
出处
《仪表技术与传感器》
CSCD
北大核心
2015年第8期57-61,共5页
Instrument Technique and Sensor
基金
广西科学基金项目(2014GXNSFAA118392)
广西教育厅科研项目(2013LX092)
