摘要
设计了一款符合EPC C1 G2/ISO 18000-6C协议的超高频射频识别标签数字基带处理器。采用新型数字基带结构,并运用门控时钟、异步计数器和多种低频时钟协同工作等多种低功耗设计方法,降低了标签芯片的功耗和面积。在TSMC 0.18μm标准CMOS工艺下流片,数字基带处理器版图面积为0.14mm2,数字部分平均功耗为14μW。
A baseband processor for UHF RFID tag based on EPC C1 G2/ISO 18000-6C protocol was presented. In order to minimize the power consumption and cost, a novel digital baseband architecture was proposed and a series oI low power design approaches were adopted, including clock-gating, asynchronous counter and multiple low operating frequency, etc. The whole tag was fabricated in TSMC 0. 18 〉m standard CMOS technology. The digital processor occupied an area of 0.14 mm^2 and the real measurements on the final chip indicated that the average power consumption was 14 μW.
出处
《微电子学》
CAS
CSCD
北大核心
2015年第5期568-572,共5页
Microelectronics
基金
北京市科委科技计划项目(E141100006014032)
