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应用于LTE通信系统中专用Viterbi译码器实现

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摘要 提出了一种应用于LTE中的(3,1,7)专用Viterbi译码器ASIC实现方案,采用全并行的加比选结构,性能分析结果表明,基于SMIC 55nm工艺,该译码器在时钟频率为185MHZ情况下,使用Synopsys Design Compiler对RTL代码进行逻辑综合,得到面积为0.125mm2,功耗仅为1.7mw。
作者 黄昊
出处 《电子技术与软件工程》 2015年第22期44-45,共2页 ELECTRONIC TECHNOLOGY & SOFTWARE ENGINEERING
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