摘要
本文提出了在FPGA平台实现一个高速的4096点的FFT处理器的设计方案。该方案采用了基8算法和流水线结构,提高了FFT的运算速度,节省了FPGA内部的乘法器资源。结果表明,在FPGA时钟频率大于100MHz的条件下,完成了4096点FFT运算,满足了现有TD-LTE系统数据吞吐率的要求。
This paper presents the design scheme of a high speed 4096 point FFT processor on the FPGA plat- form. The scheme uses the 8 point algorithm and pipeline architecture, which improves the speed of FFT operation and saves the resources of FPGA. Under the condition that the FPGA clock fxequency is more than 100MHz, 4096 point FFT operation is completed, and data throughput rate of the existing TD-LTE system is satisfied.
出处
《科技广场》
2015年第12期15-17,共3页
Science Mosaic
