摘要
针对现代数据传输速度越来越快、数据量越来越大的现状,提出了基于CML数据传输标准的高速数据传输电路的设计。以FPGA为主控制器,协议芯片选用接口标准为CML的内部编码方式为8 b/10 b编码的TLK1501芯片,以此实现高速数据传输。在FPGA中对时钟信号进行了时序约束实现逻辑控制的修正,解决了因内部时钟占空比失真而导致产生误码的问题。电路经试验验证,具有较高的稳定性和可靠性。
A design of high-speed data transmission circuit based on the CML data transfer standard was proposed, which is an important developing for the present situation of the increasingly larger amount of data and faster data transmission speed. The circuit combines FPGA controller and TLK1501 as protocol chip whose internal encoding method is 8 bit/10 bit and interface standards is CML to realize high speed data transmission. It amended the logic control due to the timing constraints of the clock signal and solved the problem of bit errors due to the distortion of the internal clock. The experimental results show that the circuit has a high stability and reliability.
出处
《电子器件》
CAS
北大核心
2016年第1期94-97,共4页
Chinese Journal of Electron Devices
