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一种低功耗无片外电容LDO的设计 被引量:5

Design of a Low Power Capacitor-Less LDO
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摘要 基于SMIC 0.18μm CMOS工艺,设计了一款输入电压为1.8V、输出电压为1.6V的低功耗无片外电容低压差线性稳压器(LDO),其静态电流仅为5μA。该电路采用一种新型摆率增强电路,通过检测输出电压的变化实现对功率管的瞬态调节。片内采用密勒补偿使主次极点分离,整个系统在负载范围内具有良好的稳定性。仿真结果显示,该LDO在负载电流以99mA/1μs跳变时,输出电压下冲为59mV,上冲为60mV,响应时间约为1.7μs。 A low power capacitor-less low-dropout(LDO)regulator with an input voltage of 1.8Vand an output voltage of 1.2V was presented.The proposed LDO regulator had been designed and simulated in SMIC 0.18μm CMOS process,consuming aquiescent current of only 5μA.This LDO used a new slew-rate-enhanced(SRE)circuit which adjusted the power transistor instantaneously by detecting the output voltage.By miller compensation,the dominant pole and the second pole were separated to keep good stability over the load range.Simulation results showed that the amount of undershoot of the output voltage was 59 mV and the overshoot of the output voltage was 60 mV for a load slew-rate of 99mA/μs.The settling time was about 1.7μs.
出处 《微电子学》 CAS CSCD 北大核心 2016年第2期202-206,共5页 Microelectronics
基金 国家自然科学基金资助项目(61401137 61371025)
关键词 低压差稳压器 摆率增强电路 瞬态响应 静态电流 Low-dropout regulator Slew-rate enhanced circuit Transient response Quiescent current
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参考文献5

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