期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

亚阈值超低功耗数字电路研究进展

Study on Sub-Threshold Ultra-Low Power Digital Circuits
原文传递
导出
摘要 基于亚阈值的超低功耗数字电路与系统正在兴起。为了全面阐述和剖析亚阈值电路的研究状况,调研了亚阈值电路的设计发展过程,阐述了亚阈值电路设计的发展趋势。针对亚阈值电路研究中的主要问题,给出了设计实例。比较了亚阈值电路中的典型设计方法学,并针对两种设计方法分析其优势和劣势。对目前亚阈值电路的研究热点作了阐述,指出其中存在的一些问题及研究方向。 Sub-threshold ultra-low power digital circuits and system are emerging. In order to make a comprehensive analysis and elaboration of the research on sub-threshold circuits, the development process of sub- threshold circuits was surveyed, and the development trend of sub-threshold circuit design was described. Design examples were given for the main research topics on sub-threshold circuit design. The two typical design methodologies on sub threshold circuit design were compared, and their strengths and weaknesses were analyzed. The research hotspots in the field of sub-threshold circuits were elaborated, and some problems and research directions were pointed out.
作者 金威 沈国荣 何卫锋 蒋剑飞 毛志刚
机构地区 上海交通大学微电子学院 上海集成电路技术与产业促进中心
出处 《微电子学》 CAS CSCD 北大核心 2016年第3期424-428,共5页 Microelectronics
基金 上海市科学技术委员会科研计划资助项目(13511500802)
关键词 亚阈值 超低功耗 数字电路 Sub-threshold Ultra-low power Digital circuit
分类号 TN791 [电子电信—电路与系统]
  • 相关文献

参考文献22

  • 1WANG A, CALHOUN B H, CHANDRAKASAN A P. Sub-threshold design for ultra low-power systems [M]. New Youk: Springer Verlag, 2006.
  • 2JOCKE S C, BOLUS J F, WOOTERS S N, et al. A 2.6-μW sub-threshold mixed-signal ECG SoC [C] /// Symp VLSI Circ. Kyoto, Japan. 2009: 60-61.
  • 3CALHOUN B H, KHANNA S, YANQING Z, et al. System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms [C] // Proceed IEEE Int Symp Circ Syst. Paris, France. 2010: 269-272.
  • 4SWANSON R, MEINDL J. Ion-implanted complementary MOS transistors in low-voltage circuits[J].IEEE J Sol Sta Circ, 1972, 7(2) : 146-153.
  • 5KIM C H I, SOELEMAN H, ROY K. Ultra-low- power DLMS adaptive filter for hearing aid applications [J]. IEEE Trans VLSI Syst, 2003, 11 (6): 1058- 1067.
  • 6PAUL B C, SOELEMAN H, ROY K. An 8X8 sub- threshold digital CMOS carry save array multiplier [C] // Proceed 27th Europ Sol Sta Circ Conf. Villach, Austria. 2001: 377-380.
  • 7WANG A, CHANDRAKASAN A. A 180-mV subthreshold FFT processor using a minimum energy design methodology [J]. IEEE J Sol Sta Circ, 2005, 40(1) : 310-319.
  • 8HANSON S, ZHAI B, SEOK M, et al. Exploringvariability and performance in a sub-200-mV processor [J]. IEEEJ SolStaCirc, 2008, 43(4): 881-891.
  • 9CALHOUN B H, CHANDRAKASAN A. A 256 kb sub-threshold SRAM in 65 nm CMOS [C] // IEEE Int Sol Sta Circ Conf Dig Tech Pap. San Francisco, CA, USA. 2006: 2592-2601.
  • 10YU P, DE PINDER G J, CORPORAAL H, et al. An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage [J]. IEEE J Sol Sta Circ, 2010, 45(3): 668-680.
微电子学
2016年 第3期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部