摘要
针对网络信息在安全性上的需求,并结合AES加密算法运行速度快、安全性高、硬件配置要求低等特点,对AES加密算法在FPGA上的实现进行了研究。通过对AES加/解密算法的分析,给出基于FPGA的AES解密系统的总体架构,系统包括密钥扩展、控制与存储、轮变换等功能模块,用VHDL语言对各功能模块进行系统设计。实验证明:该系统实现了AES解密功能。
In view of the network information security need,and combined with the AES encryption algorithm running fast,high security,low hardware configuration requirements,the implementation of AES encryption algorithm on the FPGA is studied. Based on the analysis of the algorithm of AES encryption-decryption,the article presents the general structure of AES decryption system based on FPGA. The system includes function modules,such as the secret key extension module,the control and storage,the transformation module and so on,and the function modules are designed by using VHDL language. After the verification of the system,it realizes the AES decryption function.
出处
《成都工业学院学报》
2016年第2期27-30,共4页
Journal of Chengdu Technological University
基金
四川省教育厅基金项目"软件无线电中的加密模块研究"(15ZA0145)
