摘要
通过现场可编程门阵列(FPGA)实现了一款具有通用性的UART模块,整个系统的设计采用自顶向下的模块化设计思想以及Verilog HDL的编程语言完成,并通过串口调试助手以及Signal Tap仿真发现该系统能够准确的发送、接收数据。整个UART接口电路结构简单,工作稳定可靠,可应用于各种具有UART接口的硬件电路中。
It achieved a universal UART model, the whole system of the study is designed with the top-down modular design idea and Verilog data rightly through the works stable and reliabl HDL programming language, and fortunately, it is found that the system can send and receive simulation of Serial debugging assistant and Signal Tap. The UART interface circuit which e can be used in a variety of hardware circuit systems with the UART interface.
出处
《中国集成电路》
2016年第6期38-41,共4页
China lntegrated Circuit
基金
山东省科技攻关计划项目(2012J0030009)
